1. Field of the Invention
The present invention relates to programmable logic devices, and more particularly, to an apparatus and method which provides for the selection of output type and polarity in a programmable logic device which minimizes any resulting increase in the propagation time of the logic.
2. Art Background
Most programmable logic devices (PLD's) are internally structured as variations on an architecture which utilizes a programmable logic array. A programmable logic array makes use of the fact that any logic equation can be converted into an equivalent "sum-of-products" form and thus implemented through the use of interconnected "AND" and "OR" gates. A programmable logic device (PLD) incorporating this architecture provides the user of the PLD with the ability to programmably determine the inputs into an array of "AND" gates connected to an array of "OR" gates, and thereby, programmably determine a number of sum of product terms.
Programmable logic devices (PLD's) typically provide the user of the PLD with a number of options with respect to each sum of product term generated by the PLD. For example, a PLD frequently provides for the option of feedback wherein selected sum of product terms can be coupled back into the programmable logic. In addition, a PLD also frequently provides for the ability to output the complement of a sum of product, or a registered version of a sum of product such that sequential logic can be programmed. Providing for these output options, however, tends to disadvantageously add to the overall propagation time of the logic due to the addition of further stages of circuitry. As will be described, the apparatus and method of the present invention advantageously provides for output type and polarity selection in a PLD, while minimizing any addition to the overall propagation time of the logic.